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[Other resource] abel-hdl

Description: lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
Platform: | Size: 660718 | Author: evan | Hits:

[ELanguage] voice-cpld

Description: 在CPLD内实现声调和时间的控制，在LATTICE的ISPLEVER6.1下编译通过。可以修改定时时间进行声调的修改
Platform: | Size: 2039 | Author: yangyiping | Hits:

[VHDL-FPGA-Verilog] 并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)

Description: 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
Platform: | Size: 2302730 | Author: mikeldm@163.com | Hits:

[VHDL-FPGA-Verilog] 1032yiwei_new

Description: CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code
Platform: | Size: 2048 | Author: 冯达 | Hits:

[VHDL-FPGA-Verilog] abel-hdl

Description: lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
Platform: | Size: 660480 | Author: evan | Hits:

[VHDL-FPGA-Verilog] ispLEVER培训教程

Description:
Platform: | Size: 1047552 | Author: evan | Hits:

[Other] CPLDoptimize

Description: lattice cpld优化技巧资料，无需密码，下载即用！-lattice cpld optimization techniques, without password, download and use!
Platform: | Size: 297984 | Author: 邓丰涛 | Hits:

[Other] ISPdownload

Description: 各种JTAG：包括ALTERA、ARM、AVR、LATTICE、S52、XILINX。-various JTAG include : Altera, ARM, AVR, LATTICE, S52, XILINX.
Platform: | Size: 182272 | Author: 郭shaojia | Hits:

[Books] FPGAusingall

Description: 针对CPLD的所有应用，使自己花了好长时间才整理出来，分类-CPLD for all applications, so that spent their time before finishing well out of classification
Platform: | Size: 16572416 | Author: 阚建峰 | Hits:

[VHDL-FPGA-Verilog] trafic

Description: CPLD lattice1032 VHDL实现交通灯控制！-CPLD lattice1032 VHDL to achieve control of traffic lights!
Platform: | Size: 144384 | Author: 徐家汇 | Hits:

[Other Embeded program] PLDDOWNL

Description: LATTICE公司的CPLD/FPGA的ISP下载电缆PCB设计图。-LATTICE company s CPLD/FPGA s ISP download cable PCB design.
Platform: | Size: 29696 | Author: 吕常智 | Hits:

[ARM-PowerPC-ColdFire-MIPS] DS1002

Description: lattice CPLD 芯片资料，网上不好找，我分享给大家
Platform: | Size: 581632 | Author: wanwenqing | Hits:

[Embeded-SCM Develop] LatticeDownload

Description: 最流行的CPLD，Lattice下载电缆图纸。-The most popular CPLD, Lattice download cable drawings.
Platform: | Size: 65536 | Author: 王飞 | Hits:

[ELanguage] voice-cpld

Description: 在CPLD内实现声调和时间的控制，在LATTICE的ISPLEVER6.1下编译通过。可以修改定时时间进行声调的修改-In the CPLD to achieve control of tone and time, in LATTICE under the ISPLEVER6.1 compiled through. Can be modified from time to time time to tone changes
Platform: | Size: 2048 | Author: yangyiping | Hits:

[VHDL-FPGA-Verilog] music

Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。 -Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
Platform: | Size: 8192 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] colorful_signal

Description: 设计并调试好一个VGA彩条信号发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 由系统提供的时钟源引入扫描信号，根据VGA彩色显示器的工作原理，设计出各种颜色编码和行场扫描信号。将并口线从计算机并口与CPLD/FPGA适配板连接好，然后将VGA接口与彩色显示器连接好，彩条信号就可以在显示器中产生，通过按键可以改变产生彩条的方式，共六种彩条信号，两种横彩条，两种竖彩条，两种棋盘格。本实验运用层次化设计出VGA彩条信号发生器，由行场信号模块模块和彩条信号发生模块构成，彩条信号发生器的顶层原理图如图10.7 所示. -err
Platform: | Size: 7168 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] MICO8_DEMO_03_18_08.ZIP

Description: Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。-Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to support the GCC compiler. Lattice can all FPGA and MachXO devices use. In this case contains examples and documentation. On the use of Lattice devices users or learning CPU design personnel have a higher reference value.
Platform: | Size: 3317760 | Author: ymjcloud | Hits:

[VHDL-FPGA-Verilog] A01

Description: 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilinx, Lattice, Altera and other manufacturers of the CPLD/FPGA.
Platform: | Size: 3234816 | Author: 李德明 | Hits:

[Software Engineering] Userguide(1)

Description: lattice 的CPLD 资料 lattice 的CPLD 资料-lattice of the CPLD data
Platform: | Size: 1683456 | Author: zsg | Hits:

[Program doc] CPLD

Description: 基于lattice的CPLD时钟除频的编程与设计。-Lattice-based CPLD clock divider programming and design。
Platform: | Size: 1024 | Author: 陈祥 | Hits:
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